1. Field of the Invention
The present invention relates to a semiconductor memory device having six-transistor configuration static random access memory (SRAM) calls or other memory cells of a complementary-metal-oxide-semiconductor (CMOS) configuration and a method of producing the same, more particularly relates to a semiconductor memory device which improves the memory cell characteristics by reducing the fluctuation in transistor characteristics due to misalignment of the pattern and by reducing the resistance of the interconnections and which increases the flexibility in layout of interconnections of storage nodes for connection inside the cells and thereby reduces the area of the same and to a method of producing a semiconductor memory device enabling close arrangement of interconnections of storage nodes.
2. Description of the Related Art
An SRAM cell is in general comprised of a flip-flop and two transistors (so-called word transistors) controlled to be conductive or nonconductive in accordance with a supply voltage of a word line and determining whether to connect the two storage nodes of the flip-flop to a bit line. It can be broadly divided into two types according to the difference in the load elements of the flip-flop: a metal-oxide-semiconductor (MOS) transistor load type and a high resistance load type. Of these, the MOS transistor load type has a six-transistor configuration. Depending on the type of the load transistor, a p-type channel NOS transistor (hereinafter referred to as a p-MOS) load type and a thin film transistor (TFT) load type are known.
Looking at a first related art, FIG. 80 is a plan view of an example of the pattern of the layout of a p-MOS load type SRAM cell according to the related art. FIG. 80 shows the state after forming the gates of the transistors and omits the illustration of the connections inside the cell and the upper-layer interconnections of the bit lines etc. Instead, FIG. 80 shows connection of portions connected by the upper-layer interconnections overlappingly on the pattern diagram.
In FIG. 80, reference numeral 300 shows the p-MOS load type SRAM cell, 302a and 302b show p-type active regions in which MOS transistors having n-type channels (hereinafter referred to as n-MOS) are to be formed, and 304a and 304b show n-type active regions in which p-MOS's are to be formed. The areas surrounding the active regions 302a, 302b, 304a, and 304b form element isolation insulating regions using local-oxidation-of-silicon (LOCOS) or trenches.
In this SRAM cell 300 of the related art, the two p-type active regions 302a and 302b have planar shapes bent outward substantially perpendicularly. At the two sides straddling each of the bent portions are formed a drive transistor Qn1 (or Qn2) and a word transistor Qn3 (or Qn4). A word line serving also as the polycrystalline silicon gate electrodes of the word transistors Qn3 and Qn4 is laid intersecting both of the two p-type active regions substantially perpendicularly and running between cells in the horizontal direction in FIG. 80. As opposed to this, common gate lines 306a and 306b serving also as polycrystalline silicon gate electrodes of the drive transistors Qn1 and Qn2 are formed separately for each cell. That is, the common gate line 306a perpendicularly intersects the p-type active region 302a in the vertical direction in FIG. 80, while the common gate line 306b perpendicularly intersects the p-type active region 302b in the same direction.
These common gate lines 306a and 306b perpendicularly intersect the n-type active regions 304a and 304b, respectively, as wall. Due to this, a p-MOS (load transistor Qp1 or Qp2) is formed at each of the n-type active regions 304a and 304b. The load transistor Qp1 and the drive transistor Qn1 constitute a first inverter, while the load transistor Qp2 and the drive transistor Qn2 similarly constitute a second inverter. Note that each common gate line 306a and 306b has a branch line near the mid portion. As shown by the connections in FIG. 80, an input of one inverter is connected to the output of the other inverter by a second-layer polycrystalline silicon layer. Further, a supply line of a power voltage V.sub.cc, a supply line of a common potential V.sub.ss, and bit lines BL1 and BL2 are connected as shown in the figure.
Looking at a second related art, in recent years, for example, "A LOW COST MICROPROCESSOR COMPATIBLE, 18.4 .mu.m.sup.2, 6-T BULK CELL TECHNOLOGY FOR HIGH SPEED SRAMS. VLSI Symposium Report, pp. 65-66, 1993" proposed a split word line type SRAM cell with word lines laid split for each word transistor.
FIG. 81 is plan view of the pattern of the layout of the split word line type cell described in that paper and is shown in the same way as FIG. 80.
In the split word line type SRAM cell 310, a p-type active region 312 in which n-MOS transistors are to be formed it formed in common between the inverters and word transistors and is made common between cells adjoining in the word line direction as well. In the same way, an n-type active region 314 in which p-MOS transistors are to be formed is formed in common between inverters and between cells adjoining in the word line direction.
Note that, the connections shown in FIG. 81 are basically the same as those in FIG. 80, but here the serial connections of the p-MOS's and n-MOS's of the inverters are comprised by second-layer polycrystalline silicon layers, the connections between the serial connecting points and the inputs of the other inverters, the supply line of the power voltage V.sub.cc, etc. are comprised by third-layer polycide layers, and the supply line of a common potential V.sub.ss and the bit lines are comprised by fourth-layer metal interconnections.
Turning now to the problems to be solved by the invention, in general reduction of the pattern size is indispensable in increasing the degree of integration and the memory capacity of semiconductor memory devices. This reduction of the pattern size is achieved by forming finer patterns, reducing the amount of mismatch in alignment of photo masks between different patterns, and adopting self-alignment technology where mismatch between patterns does not become a problem.
At the present time, the former finer patterns are formed by improving the resist materials, increasing the precision of producing of the interconnections etc. using the resist as a pattern transfer mask, and shortening the wavelength of the light emitted from the exposure system from g-rays to KrF excimer lasers, ArF excimer lasers, and on to X-rays.
On the other side, looking at the latter mismatch between patterns, the amount of mismatch can be tremendously reduced while maintaining high characteristics and reliability by adopting self-alignment technology. In the actual manufacture of devices, however, the types of processes in which self-alignment technology can be applied are limited. In other processes, the amount of mismatch between patterns depends on the mechanical precision of the exposure system. The mechanical precision cannot be improved to a great degree, so the amount of mismatch is not being reduced at the same pace as the miniaturization of the patterns themselves at the present time.
Therefore, it is required to design patterns so that even if mismatch occurs between patterns, it will not become a problem as seen from the characteristics and reliability--particularly in processes where self-alignment technology cannot be adopted.
The SRAM cells of the first and second related arts explained above with reference to FIGS. 80 and 81, however, were not designed with sufficient consideration to the mismatch between patterns.
For example, in the SRAM cell 300 of the first related art shown in FIG. 80, the p-type active regions 302a, 302b for forming the n-MOS's are bent outward. Despite the patterns on the mask being patterns of combinations of rectangular shapes, the actually produced pattern ends up becoming deforming with the corners become very rounded as shown. This occurs due to the excessive light intensity in the case of pattern formation by leaving the resist and insufficient light intensity in the case of pattern formation by removing the resist when using a mask pattern for exposure on a resist (transfer of pattern). In the specific case illustrated, the drive transistors Qn1 and Qn2 tend to increase in gate width (size of overlay perpendicularly intersecting channel current direction) and the word transistors Qn3 and Qn4 tend to decrease in gate width.
Further, in addition to the pattern deformation, the patterns of the p-type active regions themselves are bent. When forming gate electrodes (in this case, the word line WL and the common gate lines 306a and 306b) on them, the mismatch of the photo masks ends up causing fluctuations in the transistor size (size of channel formation region).
For example, in FIG. 80, if the gate patterns of the common gate lines 306a, 306b etc. are is offset to the right with respect to the patterns of the p-type active regions 302a, 302b (actually, the LOCOS patterns), the gate width of the drive transistor Qn2 will decrease and the gate width of the drive transistor Qn1 will increase. Conversely, if the gate patterns are offset to the left, the gate width of the drive transistor Qn1 will decrease and the gate width of the drive transistor Qn2 will increase. In both cases, this will result in the characteristics of the two inverters constituting the flip-flop becoming unequal and will result in a drop in the stability of the flip-flop and further the data retention characteristic of the SRAM memory cell.
Further, if a gate pattern is offset downward, the gate widths of the word transistors Qn3 and Qn4 will both become smaller. Accordingly, when reading from or writing to the SRAM memory cell, the resistance of the path of the cell current flowing from the bit line to the word transistor, the storage node, the drive transistor, and then the common potential supply line will become larger, especially at the "low-node" side held by a low potential level, therefore the read or write operation become slower. Conversely, when the gate pattern is offset upward, while there is no problem with the cell shown in FIG. 80, in the adjoining cell above FIG. 80 arranged vertically symmetrically across from the cell contact, the same thing happens as with the gate pattern being offset downward in FIG. 80 and as a result, the resistance of the path of the cell current increases and the read or write operation becomes slower.
In this way, if the sizes at the n-MOS side change, that is, the sizes of the drive transistors and the word transistors change relative to each other, the cell characteristics (data retention characteristic, high speed, etc.) will become lower.
Further, the amount of mismatch of patterns differs slightly depending on the location in the wafer (for example, by each chip), therefore the change in characteristics also changes depending on the location in the wafer. This shows up as differences in characteristics of the finished semiconductor devices in the memory cell array or between chips.
The problem of the reduction in of fluctuation of characteristics arising due to the translator sizes also occurs in the split word line type SRAM cell shown in FIG. 81.
In the split word line type SRAM cell 310, the active regions 312, 314 are commonly connected between adjoining cells. The commonly connected portions are bent with respect to the other portions, so the change in size at both the drive transistors Qn1, Qn2 and the load translators Qp1, Qp2 adjoining the bent portions becomes a problem. In particular, this type of SRAM cell is susceptible to mismatch in the direction in which the bit lines are laid and differences easily occur between inverters. In this case as well, the data retention characteristic of the memory cell and the read or write speed fall.
The problems of the decline and fluctuation in these characteristics can be avoided by arranging the gate electrodes sufficiently away from the bent parts of the active regions, but this increases the cell area and therefore is not desirable.
Note that, in the related art, the power voltage supply line was formed by a metal interconnection, but, for example as shown in FIG. 81, it was necessary to lay the power voltage supply line at a pitch of the same extent as the LOCOS or first-layer polycrystalline silicon interconnections (word lines WL1, WL2 or common gate lines 316A, 316B). In this case, in high-resolution patterning, while the resist film becomes thinner, since it is necessary to secure a certain thickness of the resist film remaining after etching, the metal interconnection for forming the power voltage supply line cannot be made too thick. For example, if the thickness of the resist at this time is made 0.7 .mu.m in the same way as when forming the LOCOS or the first-layer polycrystalline silicon interconnections, the thickness of the metal interconnection for forming the power voltage supply line has to be made no more than 200 nm.
With a metal interconnection of a thickness of no more than 200 nm, however, the material of the interconnections becomes limited to a titanium-based material in view of the required resistance to electro-migration (EM). As a result, there is the problem that the resistance of the power voltage supply line cannot be lowered.
To avoid this problem, if trying to form the metal interconnections by the low resistance Al, it is necessary to make the total thickness of the metal interconnections, including the anti-reflective coating and barrier metal provided above and below the Al, 400 nm in view of the EM resistance. In this case, it is necessary to make the thickness of the resist at the time of patterning the interconnections at least two times that when patterning the first-layer polycrystalline silicon layers (for example, at least 1.4 .mu.m). Therefore, the pitch of the Al interconnections has to be made about 1.5 times larger than the first-layer polycrystalline layers.
For example, in the example of FIG. 81, assuming the sizes of the cell in the x- and y-directions to be substantially the same, it is too considerably difficult to arrange 2.5 fourth-layer metal interconnections by Al interconnections in a size of one side of the same cell where four first-layer polycrystalline silicon layers are arranged.
In the cell pattern shown in FIG. 81, the size of the cell in the bit line direction was determined by the first-layer polycrystalline silicon layers, therefore further reduction of size is difficult unless these can be made finer in pattern.
On the other hand, the size of the cell in the word line direction was determined by the pitch of the second-layer and higher interconnections. Therefore, to reduce the resistance of the power voltage supply line, due to the above-mentioned restrictions on the material and pitch of the interconnections, it is necessary to further increase the number of layers of the interconnections. Increasing the number of layers of the interconnections, however, would not only make the producing process more complicated, but would also significantly detract from the cost-reducing effect resulting from the reduction of the cell size or conversely cause the cost to increase and therefore is not desirable.